The Cell architecture is looking very interesting. The eight SPE's communicate with each other and the main processor core over a 16GB/sec EIB (Element Inerconnect Bus) - and the processor supports up to 64GB of memory. Supposedly RAMBUS XDR (Extreme Data Rate) memory will be used in the PS3.
Today we also learn that you can apparently connect two cell processors without glue logic, for a simple two way SMP Cell system; and that there is a mechanism for connecting several two way nodes togeather to form larger multi-processor systems.
Apparently engineering samples have been clocked as high as 5.2GHz - no mean feat given that the design goal was apparently 3.2GHz.
Given the unique architecture of the Cell, it is most suited to applications that need to process vast quantities of floating point data; as such it is suitable for 3D gaming and visualization, modeling and scientific computing uses. With the new details emerging about multi-processing capabilities of the platform, I would not be surprised if IBM targeted the supercomputer market with massively parallel Cell systems. I do consider it unlikely that people will use Cell's for database, file or web servers as it would waste the capabilities of the eight SPE cores on each processor.