General Discussion 11 again: Now with twice the enchanting musk - Page 8

quote hiigaran

okay i got the webcam - now i need a program that can record. any recommendations?

quote MRN0B0DY

What is Overclocking?

quote harbin91

Back again. So I'm now near enough settled on the build, but one question is that I've been looking at the new AMD FX8120. Was considering it aswell, until I found reviews and saw that it was considered inferior to the X6, and is beaten in performance by the i5 2600k. Question is now, I can pick up an X6 1100T for around £60 more than the X4. Would the £60 extra be worth two cores? Would two cores make a difference?

I shouldn't need to alter anything else of the build if I do, right? I've checked the motherboard and that is fine with an X6.

quote harbin91

Side note, can someone explain how RAM performance is worked out? Only that from what I can see the main things that affect how good RAM is is the latency timings and the RAM Speed. How do these affect how good RAM is as I've seen RAM with a slower speed but have a lower latency time. I'm not exactly sure how you work out which latency is better:

E.G. 9-9-9-24, 7-8-7-24, 8-8-8-21...

quote masterslair.com

1st number CAS Latency (tCL) – This is the most important memory timing. CAS stands for Column Address Strobe. If a row has already been selected, it tells us how many clock cycles we’ll have to wait for a result (after sending a column address to the RAM controller).
2nd number Row Address (RAS) to Column Address (CAS) Delay (tRCD) – Once we send the memory controller a row address, we’ll have to wait this many cycles before accessing one of the row’s columns. So, if a row hasn’t been selected, this means we’ll have to wait tRCD + tCL cycles to get our result from the RAM.
3rd number Row Precharge Time (tRP) – If we already have a row selected, we’ll have to wait this number of cycles before selecting a different row. This means it will take tRP + tRCD + tCL cycles to access the data in a different row.
4th number Row Active Time (tRAS) – This is the minimum number of cycles that a row has to be active for to ensure we’ll have enough time to access the information that’s in it. This usually needs to be greater than or equal to the sum of the previous three latencies (tRAS = tCL + tRCD + tRP).