Core 2 Extreme QX9650 Launch & Review - 45nm Yorkfield aka Penryn is here! - PAGE 2William Henning - Monday, October 29th, 2007
Changes to Architecture
Intel is pulling no punches with its Penryn core. Some of the changes they've implemented are targetted directly at server platforms, while others are generally useful alround.
L2 Cache changes
The L2 cache has been increased to 6MB, a 50% increase, with 24 way associativity. Quad core packages will therefore have a total of 12MB of L2 cache, further reducing the number of cache “misses” that will be encountered by most software.
The “split load” capability will reduce the current penalty for reading a data item where parts of the item are located in two different cache lines.
Radix-16 Divider
By doubling the number of quotient bits computed in each iteration of a division instruction from two bits of quotient to four, integer and floating point divide (and modulus) operations are doubled in speed.

Virtualization
The improved virtualization entry and exit times – averaging a 25% to 75% gain – will lower the overhead for virtual machines, and as virtualization is becoming common in server space, it is a welcome optimization. Neoseeker itself earlier this year had replaced 2 of its servers with new virtual servers running a total of 5 VM's, and we know other sites that have gone this route, so virtualisation is something all of you are using indirectly every day and is an especially exciting topic for new CPUs.

Store Forwarding & Improved OS synchronization support:
Store forwarding allows a read of a memory location to occur from the write pipe even if a mis-aligned write to main memory has not occurred yet; interrupts can be enabled and disabled faster and locked instructions can also execute faster – this should be a benefit in high I/O interrupt situations such as database servers.
Deep Power Down Technology
A new power management state significantly reduces power consumption during idle periods by adding a deeper “sleep” state that flushes caches, saves internal micro-architecture state and shuts off power to inactive cores and their L2 cache.
Dynamic Acceleration Technology
When one or more cores are inactive, the performance of an active core can be automatically boosted while still remaining within the power envelope of the chip – this basically sounds like automatically overclocking some active cores when other cores are inactive, so for example, on a quad core system, if two cores were idle during game play, the two active cores speed would automatically be boosted.