DFI LanParty nF4 SLI-DR - PAGE 4Terren Tong - Monday, March 21st, 2005
BIOS Settings at a Glance
The nF4 BIOS is pretty complex and we've done our best to summarize the different settings available with most of the enthusiast settings. We will go into some commentary about the BIOS on the following page but here is summary of settings available on the nF4 SLI-DR (most of which relate to memory).
| FSB Bus Speed | 200-456 Mhz in 1 Mhz increments | | HyperTransport Ratio | 1-3 in 0.5 steppings 3-5 in integer steppings | | HyperTransport Bandwith | 8/8, 16/8, 8/16, 16/16 | | CPU Multiplier Ratios | 4 to CPU Max in 0.5 steppings | | PCI Express Frequency | 100-145Mhz in 1 Mhz steppings | | CPU Voltage | 0.800-1.550 in 0.0125v steppings; voltage multiplier settings 1.00, 1.04, 1.10, 1.13, 1.23, 1.26, 1.33, 1.36 | | HyperTransport Voltage | 1.20v to 1.50v in 0.1v steppings | | Chipset Voltage | 1.5v to 1.8v in 0.1v steppings | | DRAM Voltage | 2.5v to 4.9v in 0.1v steppings | | Memory Divider | 1:2, 3:5, 2:3, 7:10, 3:4, 5:6, 9:10, 1:1 | | Command Per Clock | On/Off | | CAS Latency Control (TCL) | 1.0-4.5 in 0.5 steppings | | RAS Latency Control (TCL) | 0-7 Bus Clocks | | Min RAS active time (Tras) | 0-15 Bus Clocks | | Row Precharge Time (Trp) | 0-7 Bus Clocks | | le time (Trc) | 7-22 Bus Clocks | | Row Refresh Cycle Time (Trfc) | 9-24 Bus Clocks | | Row to Row Delay (Trrd) | 0-7 Bus Clocks | | Write Recover Time (Twr) | 2-3 Bus Clocks | | Write to Read Delay (Twtr) | 1-2 Bus Clocks | | Read to Write Delay (Trwt) | 1-8 Bus Clocks | | Refresh Period (Tref) | 16-4708 Cycles; varied stepping size | | Write CAS Latency (Twcl) | 1-8 Bus Clocks | | DRAM Bank Interleave | On/Off | | DQS Skew Control | Increase/Decrease Skew | | DQS Skew Value | 0-255 | | DRAM Drive Strength | Level 2-8 | | DRAM Data Drive Strength | Level 1-4 | | Max Async Latency | 1-15ns | | Read Preamble Time | 2-9.5ns in 0.5 ns steppings | | Idle Cycle Limit | 0-256 Cycles; stepping increments are double the previous value | | Dynamic Counter | Enable/Disable | | R/W Queue Bypass | 0,4,8,16 | | Bypass Max | 0-7 | | 32 Byte Granularity | 4 or 8 Bursts |
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