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- Tue, May 21
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What about servers?
Intel wants to make a big push to recover the market share it lost to AMD Opterons in server space. The problem is that until Intel gets away from having a shared FSB for its processors, it is inherently hobbled compared to AMD's HyperTransport interconnection scheme; something that is especially evident in systems with more than two processors.
Intel Marketing has put out a slide showing the new quad core server chips as being 50% better than existing Xeon 5100 - which are actually Core 2 Duo's in a 771 pin LGA package. Overall, given moderate to high server loads, 50% may actually be a reasonable estimate of the speedup you would get from going to quad core processors per socket on an Intel platform.
Intel also put in a line claiming 150% better performance than the competition - and stated that the estimate was based on SpecInt compared to a dual core Opteron. I can actually believe this, as it compares a quad core Intel processor to a dual core AMD processor, for an integer benchmark that is not a memory bandwidth hog.
The situation would be different comparing a four processor 5100 based system to a four processor Opteron system with a workload that was memory bandwidth hungry.
Intel is quite aware of the memory bandwidth limitations of the front side bus - and did something clever about it with the "Bensley Platform" - their dual FSB quad memory channel chipset for servers.
To put it simply, the chipset has TWO front side busses, one for each processor socket, and four memory channels.
This increases the potential memory bandwidth to 21GB/sec, and also allows up to 21GB/sec traffic (10.5GB/sec per socket) to the processors in order to work around the FSB bottleneck; and this was a simpler and quicker solution than replacing the FSB with something like CSI (Intel's upcoming alternative to Hypertransport), leading to faster time to market.
The downside is that I don't even want to think about how many pins the Northbridge must have...
Four socket platforms will still be crippled by the FSB, and if you notice the chart above, the bandwidth to the processors is given in a smaller font size than before - why?
The answer is simple. It looks like for four processor socket systems, Intel has to drop the FSB to 800MHz - and two 800MHz FSB's will give you the 12.8GB/sec theoretical bandwidth indicated above. They had to reduce the bus speed to accomodate the four loads placed on the bus by the two dual die sockets; also please note that cache coherency traffic between all the dies will be going over the shared FSB as well, reducing the bandwidth available for memory traffic.No, its not a mistake - a two socket Intel motherboard will have almost twice the potential bandwidth available to two quad core processors that a four socket motherboard will make available for four quad core processors. A quad socket Opteron motherboard will by comparison have 12.8GB/sec * 4 = 55.6GB/sec of memory bandwidth available, PLUS significant additional bandwidth from the Hypertransport links... but will be limited to just 8 cores over the four sockets (until K8L shows up) compared to Intel packing 16 cores into four sockets.
Intel showed some of the big software vendors who are building multi-core friendly software that can take advantage of quad core processors.
The server roadmap shows us a taste of things to come...
Intel has not given up on Itanium, and will be bringing out Montvale in roughly mid 2007, followed by Tukwila and later Poulson. Frankly, I wish they would use those resources to improve their x86 lineup by introducing CSI and on-chip memory controllers.
In the 7000 series, we get Tigerton mid next year, followed by Dunnington; and its a pretty safe bet that Intel will be concentrating on increasing the number of cores and improving their chipsets.
The 5000 series gets the Quad Core 5300's about now, and "Future Product" after 2007. I'd guess 8 cores in 2008.
For their UP platform, Quad Core 3200's will show up around January, with future products in 2008 and beyond.

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We only report overclocked results that we find stable to our satisfaction; we often hit higher overclocks during testing, but unless its stable, we don't really count it.
In our Asus P5W DH review, I managed to get an E6400 up to 3.64GHz - which is a very respectable overclock for an air cooled system.
With extreme cooling, I am sure I could have gotten the QX6700 higher, however I was experiencing thermal shutdowns above 3.45GHz when under sustained heavy load.
For instance in this case out of 3-4 sites we have one of the highest overclocks (Anand only got 10Mhz more than we did).
Meh this is going to be a very interesting set of months and i wana see how Amd fairs to hehe.
But seriously the Quake 4 testing should show some large improvements where the COD2 isn't so definite given that the original focus of the patch for COD2 was based around the hyper-threading marketing blitz they had going on in the 4 and D series Pentiums. Come on, you know you wanna show us those benches.
I'm confused about the conclusion as concerns DDR2 timings.
It says: In order to run at 3.45GHz we:
.....
set the DDR2 timing to 5-5-5-15 @ 1035MHz
and set the DDR2 timing to 4-4-4-12 @ 863MHz and below
Which DDR2 timing was used: 5-5-5-15 or 4-4-4-12 to achieve 3.45GHz?
Thanks,
Stuart,
The site:
http://www.ugn.com.au/joomla/index.php?option=com_content&task=blogsection&id=0&Itemid=9
regards, SgtBatten, Papadon and AssAssinX
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