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Over the last few months there has been a lot of talk on the net about Intel's upcoming Conroe processors. Intel marketing did a very good job of building interest before the launch - staging public demonstrations where Conroe was shown to be 20%-40% faster than AMD's fastest parts.

Can those claims be true?

Does Intel really have that much of an edge?

Today we can finally bring you information on Intel's new mainstream processor - the Core 2 Duo, formerly known by the code name "Conroe".

We would like to thank Gigabyte for providing us with a pre-production GA-965P-DQ6 motherboard and Core 2 Duo E6700 for testing. We will publish a preview of that motherboard shortly.

Intel will initially be releasing the following versions of the Core 2 Duo (Conroe):

• E6300 at 1.86GHz with 2MB of shared L2 cache - $221
• E6400 at 2.13GHz with 2MB of shared L2 cache - $266
• E6600 at 2.40GHz with 4MB of shared L2 cache - $368
• E6700 at 2.67GHz with 4MB of shared L2 cache - $610
• X6800 at 2.93GHz with 4MB of shared L2 cache - $1117

The above pricing in USD is the actual pricing we found hidden in a nationwide computer webstore and will likely reflect a very close ballpark figure for each of those parts.  At a later date, Intel will also offer a "budget" Core 2 Duo, the E4200, running at 2.66GHz with 2MB of shared L2 and an 800MHz FSB

Now before you are disappointed that we are "only" looking at an E6700 and not an X6800... you should know that we managed to overclock the E6700 far beyond the X6800's stock performance level! Be sure to check out our stock benchmarks and Architectural background first however.

Overview

Intel revealed some information about the Core micro architecture during the last Intel Developers Forum - here are some of the highlights:

The Core 2 Duo packs two highly efficient cores onto a single 65nm die. The two cores share a 2MB or 4MB L2 cache, and have either an 800MHz or 1066MHz FSB.

Using a single shared L2 cache instead of separate L2 caches can help as it simplifies cache coherency, and allows the two cores to use different amounts of L2 cache - with the amount being used by each core changing over time based on memory utilization. Unfortunately there are also a couple of potential disadvantages - namely contending for access of the shared L2 cache (unless it is fully dual ported; unfortunately I don't currently know if it is fully dual ported), and cache trashing - where the two cores, if both are running applications that access large amounts of memory, can be "clobbering" the whole cache in turn, repeatedly, thus significantly reducing the effectiveness of the cache.

[Dual porting memory means giving two separate ports (for the two cores) to access the memory. Ideally, both cores could access any unique cache line without having to wait; but most dual ported memory implementations "segment" the memory and both processors can access different "segments" at the same time without having to wait, but will contend over access if both try to access the same "segment" at the same time. I don't know how the L2 cache on the Conroe is segmented; but it is unlikely that it would be segmented on a 256 bit cache line basis. The finer the grain of the segmentation, the less likely the two cores are to contend over the same "segment".]