Dual Core Out of Necessity

There are several challenges facing the processor industry and not all of them are physical or process constraints though physics is definitely a mitigating factor.

One of the problems of producing ever more complex processors has nothing to do with physics or chemistry or production. The problem is man power and tossing more engineers onto design is not a solution - designers do not scale with transistors which means that a philosophy of scaling complexity is not sustainable.

This gives rise to the concept of the processor being a repeatable structure. With dual cores, the majority of silicon is replicated so while the number of transistors increase dramatically, it is a different approach than adding more functional blocks or a deeper pipeline.

Power consumption is determined by the number of transistors as well as clock speed which in turns means more heat. Dual cores allow a single processor to stay within the same general thermal and power requirements by sacrificing maximum clockspeed for much lower power consumption. While everyone is keen on reporting on how dual cores will remain in the same voltage and thermal envelope as a single core processor, it seems that there are few explanations of why this is. The following diagram shows the relationship between clockspeed and power consumption where n represents a processor with the highest clockspeed and each stepping is a 200 Mhz drop.

The relationship between power consumption and clockspeed in non-linear

A concrete example would be the FX-55 at 2.6 Ghz which would be n; n -1 would be a processor at 2.4 Ghz, n-2 would be 2.2 Ghz etc. Note that scaling back two steps is roughly a 40% reduction in power consumption. Because of the doubling of transistors however, heat output remains is actually a bit lower on the dual core 'n-2' processor when compared to a top of the line single core processor with clockspeed n.

Everyone seems to get excited when companies switch manufacturing processes like the transition from Clawhammer to Venice on AMD's high end line up which is a die shrink from 130nm to 90nm. AMD warns that the drop to 65nm is not a solution for heat output or frequency scaling as voltage does not currently scale with the process and transistor leakage is increasing.