Serial vs Parallel Connections

Just over a year ago, Serial ATA controller cards and drives began to hit the market. The tangible benefits that SATA was supposed to provide in terms of performance has not really arrived yet, but something that is noteworthy is the SATA interface compared to the old parallel ATA one; a serial ATA cable uses 8 wires while the older parallel IDE cable required an 80 pin connection (40 for transmission and another 40 as ground). One of the main problems with parallel connections are the problems when trying to scale up in speed. Signal degradation and interference become major issues (remember the 40 ground wires required in an IDE cable). A serial connection reduces the complexity of the communications protocol and reduces the pin count. This allows the speed of transmission to be pumped up significantly (theoretically SATA should be able to hit about 10 Ghz or ~1 Gigabyte/s).

PCI Express will also face the same reduction in complexity through its transition from a parallel to a serial based architecture. The design goals of PCI Express included a lower implementation cost as well, higher bandwidth per pin as well as scalable performance. The engineers behind PCI Express did not want to be caught in the same situation as with the current PCI bus; it was a robust architecture evidenced by over a decade of use and continued use for at least a couple more years but speeding up the PCI Bus is not really a feasible long term solution.

This chart from Intel shows the relative complexity of PCI, PCI-X and AGP in comparison to PCI Express (also called 3GIO, 3rd Generation I/O).

One of the cool things about PCI Express is that it's extensible in two ways- the initial spec calls for 2.5 Gb/s per direction which translates into roughly 250 MB/s per direction, roughly double the bandwidth of the current PCI bus. Remember this is available to each device with PCI Express. The second part is that for devices and slots that require high bandwidth, extra lanes can be added; x2, x4, x8, x12, x16 and x32 lanes are all possible with x16 making a debut as the next graphical bus interface.