AMD Radeon HD 7970 Launch Review - PAGE 2

Graphics Core Next is a scalable architecture designed to be optimized for both graphics horsepower and compute power. The GPU is compiled of 32 Compute Units, dual Geometry engines,  8 Render Back-Ends, 768KBs of read/write L2 cache, a 384-bit memory bus, all running on a PCI Express 3.0 x16 bus interface and packing in a total 4.81 billion transistors. Like the HD 6900 series the dual geometry engines that each have their own Rasterizer and Render Back-End units, but share the 32 Compute Units. In essence you can think of these Geometry engines as having dual cores inside the GPU.

As mentioned earlier, the Southern Islands GPU is designed to work as both a graphics and compute engine. This is due to the ACE engine which posits three devices in one GPU that are completely asynchronous from one other: the graphics pipeline, the direct compute pipeline and two parallel pipelines inside the GPU. Each of these run independently and asynchronously to the primary graphics pipeline. This allows the GPU to process an intensive compute simultaneously with the graphics pipeline at it is running an intensive 3D application, and maximizes the utilization of the available 3.71TFLOPS of compute power. Paired with this is the processing core and dual DMA engines which allow the HD 7970 to saturate the Gen 3.0 PCI-Express interface with a TeraFlop of bidirectional double precision.

On top of this, all of the GDDR5 memory is protected by single error correction, and double error detection when used in a compute environment. All the internal SRAM has the same capabilities, and also  have ECC data protection.

While many are wondering exactly how the efficiency of CGN compares to VLIW4, AMD has stated we should see an more performance per millimeter with the GCN architecture than what was available in previous generations. According to Eric Demers from AMD, the peak physical improvement over the previous generation architecture has a theoretical peak improvement of up to 7 to 7.5 times (compared to the Radeon HD 6970). The Tahiti architecture also includes an improved Gen 9 tessellator unit that increases the tessellation throughput over the previous generation via more efficient vertex re-use, larger parameter caches and improved off-chip buffering. All of this gives the GCN architecture up to 4 times the throughput in comparison to the Radeon HD 6900 series.

The basic compute unit includes all the instruction, wavefront and scheduling; essentially this unit can be thought of as its own core. Each compute unit has four sub-units that each run a way-front of 64-bit vector lanes over four cycles that are completely independent of each other. This is a huge departure from the VLIW engine, which had 5 or 4 math units that executed the individual instructions in a parallel process. Since the new GCN architecture runs fully scalar, it eliminates the compilation issues of the VLIW design.

In addition, the scalar runs in parallel to the unit and can issue instructions of its own, allowing complex operations to be moved to the scalar for improved efficiency. The unit also includes 16KB L1 cache that has both read and write functions allowing the textures to run through the cache as opposed to entering the cache to be processed and then passed on to the back-end before being exported back into the cache. This function can now be handled exclusively though the L1 cache via the read/write functions.

Moving over to this form of computing doesn't necessarily translate into improved graphics performance, but since the VLIW compiling was not necessary efficient, it will improve the total compute power, i.e. parallel processing of the GPU. The compute unit on the other hand has four independent wavefronts running in parallel as well as a scalar programing model at the lane level to ensure that all instructions running through the GPU automatically work. This eliminates all port conflicts, simplifying the compiler and instructions, thus improving the compute performance dramatically.

When it comes to the memory, each L1 cache has 64 bytes of bandwidth per clock, and the HD 7970 has a total of 32 giving it up to 2TB/s of bandwidth. As mentioned before, each L1 cache has both read and write functions, something new to the Southern Islands architecture. However, each L1 still has a L2 cache to fall back on, but the L2 also now includes both read and write functions. In total the HD 7970 comes packed with twelve L2 caches that feed back into the L1 cache which are also 64 bytes per clock. In total this gives the HD 7970 around 710GB/s of cache bandwidth with the default GPU clock speed of 925MHz for both reads and writes.

The GPU also includes a 16KB instruction cache and 32KB scalar data cache that are shared per four compute units, which as mentioned earlier are also backed by the L2 cache. Additionally, each compute unit has has its own registers and local data share. There is also a global data share unit that works as a manage buffer on the chip to allow sharing between any wavefront on the chip.

The Southern Islands architecture also includes a texture mapping technique called Partially Resident Texture, or PRT. Essentially, what this feature do is take advantage of all the memory hardware available, and turn the local frame buffer into a local texture cache. So, what does this mean? First, the local graphics memory can behave like a hardware-managed cache where texture data can be streamed in on demand. This prevents stuttering as the pages are brought in, and texture stream has the ability to handle the process more efficiently.

PRT also Improves the memory efficiency and image quality with very large, detailed textures. This allows for texture sizes up to 32 TB (16k x 16k x 8k x 128-bit). This is done by turning the textures into 64KB chunks that dynamically selects the textures that are needed to be loaded into the memory. So, essentially the textures that are not going to be displayed are not loaded. PRT also translates through the page table's every request. This allows the data to be rendered if the data is available, and if not the application can manage the textures. This allows it to dynamically opt to use lower resolution bitmaps for the lower resolution which will make the textures slightly blurry, but there will be no lag time in these situations.

Like the HD 6900 series, the Southern Islands graphics cards come equipped with AMD PowerTune technology. In essence, PowerTune is a means to set a predefined TDP by adjusting the clock speeds in real time. The way in which PowerTune is utilized is very different than the on-board regulation chips used on NVIDIA’s GTX 500 series. NVIDIA’s power management system monitors the power coming from the rails, while AMD’s technology instead relies on performance counters that are embedded throughout the GPU. These performance counters have an internal algorithm that dynamically calculate how much power is being used, and adjust accordingly. This allows PowerTune to maintain the power draw at the predefined level, effectively eliminating huge surges in power from occurring. Since games operate at a lower peak power rate than benchmarking applications such as Kombuster, in-game performance will not be negativity affected.

AMD has also introduced a new feature called "Zero Core Power" which maximizes the idle power consumption of the board. This is a potentially exciting new addition to the AMD graphics card series, and one we will touch on in the next few pages.